The present invention is generally related to an entropy encoder-decoder for fast data compression and decompression. More particularly, the present invention relates to an entropy encoder-decoder which can be used with any compression scheme that incorporates an entropy coding step.
In data transmission and processing applications it is common for data to be compressed in accordance with various compression algorithms prior to or during processing or transmission of data. Additionally, it is common for compressed (encoded) data to be decoded during or after processing or transmission to convert the encoded data back into its original form.
Some common compression schemes (or algorithms) incorporate what is known as an entropy coding step. Examples of these common algorithms which incorporate an entropy coding step include LZW, lossless JPEG, G3, G4, etc. Compression schemes which include an entropy encoding step typically generate an output-bitstream which is of variable length. Because of the variable length nature of the encoded output, processing of this data requires a great deal of computational effort on the part of the processing hardware and central processor or controller.
Typical compression hardware is generally dedicated to processing/encoding in accordance with only one pre-defined compression algorithm. Because of this limitation, if data encoded using various compression algorithms is to be processed or transmitted, it is necessary for multiple hardware implementations to be provided to accommodate each of the available compression algorithms/formats. This increases cost associated with processing or transmitting data encoded in accordance with multiple compression algorithms.
The present invention provides for encoder-decoder which can be used with any compression scheme that incorporates an entropy coding step.
The present invention provides a system and method for encoding and decoding information.
Briefly described, in architecture, the system can be implemented as follows. There is provided an encoder for encoding data comprising a data register for receiving and storing a variable length code word, bitstream register for receiving data, a multiplexor for loading valid bits from the control register into the most significant bits available in the bitstream register, a first-in-first out (FIFO) register for receiving the contents of the bitstream register when all available bits of the bitstream register are loaded with valid bits of data, and an interrupt controller for generating an interrupt signal to initiate a read out of data from the FIFO register.
In a further embodiment of the present invention there is provided a decoder for decoding data. This decoder includes a first register for receiving fixed length encoded data word data, a bitstream register for receiving the fixed length encoded data word, a multiplexor for loading variable length code word data from the bitstream buffer into a data register, and an interrupt controller for generating an interrupt signal to initiate writing of fixed length encoded data into the first register.
The present invention can also be viewed as providing a method of encoding. In this regard, the method can be broadly summarized by the following steps: receiving variable length code word data, determining the number of valid bits of the code word data, loading the code word data into a bitstream buffer if all valid bits will fit. If all valid bits will not fit into the bitstream buffer, loading a first segment of the valid bits into the bitstream buffer and then loading the contents of the bitstream register into a FIFO register, loading a second segment of the partial valid bits into the bitstream buffer.
A further method of decoding data is provided which can be broadly summarized by the following steps: receiving a data word, loading the data word into a buffer, reading out variable length code word from the data word; and loading the variable length code word into a fixed length register.